(1) Field of the Invention
The present invention relates to a method for making integrated circuits on semiconductor substrates, and more particularly to a method for forming multilevel wiring on substrates with insulators having a low dielectric constant that reduce the RC time delays. The method is particularly useful for interconnections on ULSI circuits with minimum feature sizes less than 0.5 micrometers (um).
(2) Description of the Prior Art
Integrated circuits fabricated on semiconductor substrates for Ultra Large Scale Integration (ULSI) require multilevels of metal interconnections for electrically interconnecting the discrete semiconductor devices on the semiconductor chips. In the more conventional method the different levels of interconnections are separated by layers of insulating material. These interposed insulating layers have etched via holes which are used to connect one level of metal to the next. Typically, the insulating layer is a silicon oxide (SiO.sub.2) having a dielectric constant (relative to vacuum) of about 4.1 to 4.5. However, as the device dimensions decrease and the packing density increases, it is necessary to reduce the spacing between the metal lines in the interconnections to effectively wire up the integrated circuits. Unfortunately, as the spacing decreases, the intra- (on the same metal level) and interlevel (between metal levels) capacitances increase between metal lines when an insulating layer having the same dielectric constant is used since the capacitance C is inversely proportional to the spacing d between the lines (C=keA/d where k is the dielectric coefficient, e is the permittivity of the insulator, A is the area, and d is the spacing between lines). Therefore, it is very desirable to minimize the dielectric constant k in the insulator (dielectric) between the conducting lines to reduce the RC time constant and thereby increase the performance of the circuit (frequency response) since the signal propagation time in the circuit is adversely affected by the RC delay time, where R is the resistance of the metal line, and C is the inter- and/or the intralevel capacitance mentioned above. The dependence of delays due to the gate delays and the interconnects are shown in FIG. 1 reported at the International Symposium on VLSI, TSA, 1995, page 164. As shown in FIG. 1, the curve 1 shows the time delay in nanoseconds of the FET gate minimum feature size (channel length) in um (gate delay) and the curve 2 shows the interconnect delay as a function of the minimum feature size (line spacings). It is clearly seen that as the minimum feature size is reduced below 1.0 um, the interconnection delay (curve 2) becomes the predominant circuit delay. For example, below 0.5 um the gate delay (curve 1) decreases to about 0.1 E-9 seconds while the interconnect delay 2 increases rapidly to about 2.5 E-9 seconds.
One approach to minimize these RC time delays is to use a good electrical conductor for the interconnections, such as replacing aluminium with copper to reduce resistance R, and in addition to use an insulating material that has a lower dielectric constant k, such as an organic, to reduce the capacitance C between lines. The improvement in the interconnect delay can best be understood by the family of curves in the prior art of FIG. 2 (Proceedings from the International Electronic Device Meeting (IEDM), 1995, page 244). The RC expression for a metal line L with a pitch of P and a metal thickness T and an intermetal insulating layer also having a thickness T is given by RC=2pke.sub.o (4L.sup.2 /P.sup.2 +L.sup.2 /T.sup.2), where p is the metal resistivity, k is the relative dielectric constant, and e.sub.o is the permittivity in vacuum. The family of curves is shown for the interconnect RC time delay in nanoseconds (abscissa) as a function of metal thickness in micrometers (ordinate axis) for a metal line pitch of 0.8 um and having 10 mm lengths. FIG. 2 shows the rapid increase in the interconnection delay (nsec.) as the metal thickness T is decreased for a constant pitch P and a metal length L of 0.8 um. The curve 3 is for aluminum (Al) lines having an intralevel dielectric constant k of 4, such as an undoped silicon oxide (SiO.sub.2), while curve 4 shows the improvement in delay for comparable patterned copper lines using an insulator having the same dielectric constant k of 4. Curves 5 and 6 show comparable improvement in the delay time for Al and Cu, respectively, using a low k interlevel dielectric of k=2, such as an organic polymer. For example, a number of inorganic and organic dielectrics are listed in TABLE I that can be used to reduce the RC delays.
TABLE I ______________________________________ DIELECTRIC CONSTANT ______________________________________ INORGANICS PLASMA SIO.sub.2 4.1-4.5 FLUORINE-DOPED SIO.sub.2 3.5 ORGANICS POLYIMIDE 3.0-3.7 POLYSILSEQUIOXANE (Si POLYMER) 2.7-3.0 BENZOCYCLOBUTENE (BCB) 2.7 PARYLENE N 2.7 FLUORINATED POLYIMIDE 2.5 PARYLENE F 2.3 AMORPHOUS TEFLON 1.9 ______________________________________
To better understand the problems associated with using a low dielectric polymer, FIG. 3 is shown having closely spaced metal lines 16 formed on a substrate 10 having a silicon oxide layer 12. A conformal chemical vapor deposited liner 18, such as silicon oxide, is deposited by low temperature chemical vapor deposition (CVD) to protect the metal lines from the low k polymer that typically has high moisture content. The CVD lines also serve to improve the adhesion of the low k polymer 20 which is then deposited. Typically a low dielectric polymer is deposited and planarized to provide an intermetal dielectric (IMD) layer. A hard mask 22 composed of a low temperature CVD is deposited and a photoresist mask 24 is then patterned to form the via holes in the hard mask and in the low k polymer. Typically there are several problems associated with this structure. One is the ability to control the chemical/mechanical polishing of the polymer to the top of the metal lines 16. Other problems are non-standard via hole etch, outgassing of moisture such as H.sub.2 O in the via holes that can cause via poisoning, which can erode the next level of aluminum contacts, and low dielectric breakdown strength and high electrical leakage currents. The low k polymer also has the issue of a low mechanical strength and poor dimensional stability. Another concern is poor thermal stability (&lt;450.degree. C.) that can be exacerbated by the Joule heating of the metal lines from high current density and poor thermal conductivity K of the polymers. For comparison the thermal conductivity of polymers such as polyimide, SOP (spin-on polymer), and HSQ (Hitachi Chemical polymer) are compared with the inorganic oxides plasma-enhanced PETEOS and high-density plasma (HDP) CVD in TABLE II.
TABLE II ______________________________________ Thermal Conductivity Film Thickness Dielectric Film K(mW/cm.degree. C.) (um) ______________________________________ PETEOS 11.5 0.1-3.8 HDP CVD Oxide 12.0 1.0-1.8 Polyimide 2.4 3.3-9.0 SOP 2.4 0.34-0.5 HSQ 3.7 0.27-0.38 ______________________________________
As can be seen the oxides have a thermal conductivity K as measured in milliWatts/cm.sup.o C which is about 4 to 6 times better than the polymers.
Several methods for forming planarized interconnections using low dielectric constant insulators have been described. For example, Jeng, U.S. Pat. No. 5,486,493, describes a method for forming closely spaced Al or titanium nitride/Al/titanium nitride interconnect lines having a low dielectric constant insulator between metal lines. Another method for making sub-micron metal interconnections using a spin-on glass (SOG) is described by Chen et al., U.S. Pat. No. 5,366,850, in which the SOG is cured and partially etched back to an insulating liner on the metal lines to form a planar surface. A CVD oxide is then deposited and contacts are etched to the metal lines without exposing the SOG. Chen et. al., in the Japanese Journal of Applied Physics, Vol 32 (1993) pp. 6119-6121, entitled "The Anisotropic Plasma-Enhanced Chemical Vapor Deposition SiO.sub.2 /Spin-on Glass Process for 0.35 um Technology" teaches a method for forming an intermetal dielectric for sub-micrometer metal interconnections.
As the spacings between interconnecting metal lines are further reduced, such as in future 0.18-0.13 micrometer technologies, it becomes increasingly difficult to provide an insulating layer having a low dielectric constant between adjacent metal lines and further to provide good thermal conductivity for cooling the circuit. There is also a need for providing a process with greater latitude for forming a planar low k dielectric layer, which is free of poisoned via holes (outgassing problems) that can degrade the metal contacts. Therefore there is still a strong need in the semiconductor industry for providing a simplified method for forming multilevel metal interconnections having reduced inter- and intralevel capacitance to reduce the RC time constant that improves circuit performance.